`timescale 100ps/100ps
/************************************************************************
 ************************************************************************
 ****                                                                ****
 ****    buscon.v : H8 マザーボードバス制御ロジック                  ****
 ****                                                                ****
 ****----------------------------------------------------------------****
 ****    Version 0.1 : 
 ****                                                                ****
 ************************************************************************
 ************************************************************************/
/*
 * pin assign
 *  1: TXDI ----- P15/IRQ1                   
 *  2: RxDO ----- P21/RxD
 *  3: Dummy1 --- NC
 *  4: CLKOUT --- to 5pin
 *  5: PCLOCK --- from 4pin
 *  6: Dummy2 --- NC
 *  7: SCLOCK --- GCK3/Clock(20MHz)
 *  8: WR ------- P57/SCL
 *  9: A2 ------- P56/SDA
 * 10: GND
 * 11: A1 ------- P55/WKP5
 * 12: A0 ------- P54/WKP4
 * 13: D3 ------- P53/WKP3
 * 14: D2 ------- P52/WKP2
 * 15: TDI
 * 16: TMS
 * 17: TCK
 * 18: D1 ------- P51/WKP1
 * 19: D0 ------- P50/WKP0
 * 20: PWMC
 * 21: 5V
 * 22: Dummy3 --- NC
 * 23: GND
 * 24: PWMB
 * 25: PWMA
 * 26: Dummy4 --- NC
 * 27: COMRxDI -- RxIN (from MAX232)
 * 28: COMTxDO -- TxOUT (to MAX232)
 * 29: USBRxDI -- TxIN (from FT232BM)
 * 30: TDO
 * 31: GND
 * 32: 5V
 * 33: Dummy5 --- USBTxDO
 * 34: Dummy6 --- USBTxDO
 * 35: Dummy7 --- USBTxDO
 * 36: USBTxDO -- RxOUT (to FT232BM)
 * 37: Dummy8 --- RSTOUT
 * 38: Dummy9 --- RSTOUT
 * 39: SRESET --- GSR
 * 40: Dummy10 -- RSTOUT
 * 41: 5V
 * 42: Dummy11 -- SWOUT
 * 43: SWIN
 * 44: Dummy12 -- SWOUT
 */
/*
 * JTAG pin assign
 *      +---+
 *    1 |o o| 2        1: TCK    2: Vcc(5V)
 *    3 |o o| 4        3: TMS    4: GND
 *    5 |o o| 6        5: TDI    6: GND
 *    7 |o o| 8        7: TDO
 *      +---+
 */
/************************************************************************
 *    モジュール宣言                                                    *
 ************************************************************************/
module pwmout(
    /* CPU接続 */
    D3, D2, D1, D0,
    A2, A1, A0, WR,

    /* PWM出力 */
    PWMA, PWMB, PWMC,

    /* シリアル切り替え */
    SWIN, TxDI, RxDO,
    USBTxDO, USBRxDI, COMTxDO, COMRxDI,

    /* クロック・リセット */
    PCLOCK, SCLOCK, SRESET, CLKOUT,

    /* Dummy 出力 */
    Dummy1, Dummy2
);

/**** 入出力宣言 ****/
output  PWMA, PWMB, PWMC, CLKOUT;	/* 出力端子4本 */
input	D3, D2, D1, D0, A2, A1, A0, WR;	/* 入力端子8本 */
input	SCLOCK, SRESET, PCLOCK;		/* クロック2本、リセット1本 */

input	SWIN, TxDI, USBRxDI, COMRxDI;
output	RxDO, USBTxDO, COMTxDO;
output  Dummy1, Dummy2;

/**** 属性宣言 ****/
wire		D3, D2, D1, D0, A2, A1, A0;
wire		WR, SCLOCK, SRESET, PCLOCK, CLKOUT;
wire		regAHw, regALw, regBHw, regBLw;
wire		regCHw, regCLw;
wire		Dummy1, Dummy2;
wire[3:0]	dbus;
wire[7:0]	cmpA, cmpB, cmpC;

reg		PWMA, PWMB, PWMC;
reg[1:0]	clkcnt;
reg[3:0]	regAH, regAL, regBH, regBL, regCH, regCL;
reg[7:0]	cntA, cntB, cntC;

/************************************************************************
 *    論理回路記述                                                      *
 ************************************************************************/
/**** 固定値出力 ****/
assign	Dummy1  = 'b0;
assign	Dummy2  = 'b0;
/*assign	Dummy3  = 'b0;*/
/*assign	Dummy4  = 'b0;*/
/*assign	Dummy10 = 'b0;*/
/*assign	Dummy11 = 'b0;*/
/*assign	Dummy12 = 'b0;*/

/**** 通信制御切り替え ****/
assign	RxDO = SWIN ? COMRxDI : USBRxDI;	/* 受信切り替え */
assign  COMTxDO = TxDI;				/* シリアル送信切り替え */
assign  USBTxDO = TxDI;				/* USB送信切り替え */

/**** レジスタ書き込み信号 ****/
assign	regAHw = ~A2 & ~A1 & ~A0 & ~WR;		/* Address 0x0 */
assign	regALw = ~A2 & ~A1 &  A0 & ~WR;		/* Address 0x1 */
assign	regBHw = ~A2 &  A1 & ~A0 & ~WR;		/* Address 0x2 */
assign	regBLw = ~A2 &  A1 &  A0 & ~WR;		/* Address 0x3 */

assign	regCHw =  A2 & ~A1 & ~A0 & ~WR;		/* Address 0x4 */
assign	regCLw =  A2 & ~A1 &  A0 & ~WR;		/* Address 0x5 */

/**** 出力アサイン ****/


/**** デューティ比レジスタ ****/
assign	dbus = {D3, D2, D1, D0};
always @(posedge SCLOCK or negedge SRESET) begin
    if (~SRESET) begin
        regAH = 4'b0;        regAL = 4'b0;
        regBH = 4'b0;        regBL = 4'b0;
        regCH = 4'b0;        regCL = 4'b0;
    end else begin
        if (regAHw)	regAH = dbus;
        if (regALw)	regAL = dbus;
        if (regBHw)	regBH = dbus;
        if (regBLw)	regBL = dbus;
        if (regCHw)	regCH = dbus;
        if (regCLw)	regCL = dbus;
    end
end

/**** PWMカウンタ ****/
assign	cmpA = {regAH, regAL};
assign	cmpB = {regBH, regBL};
assign	cmpC = {regCH, regCL};
always @(posedge PCLOCK or negedge SRESET) begin
    if (~SRESET) begin
        cntA = 8'b0;
        cntB = 8'b0;
        cntC = 8'b0;
    end else begin
        cntA = cntA + 1;
        cntB = cntB + 1;
        cntC = cntC + 1;
    end
end

/**** PWM 出力 ****/
always @(cntA or cmpA) begin
    if (cntA < cmpA)    PWMA = 1'b0;
    else		PWMA = 1'b1;
end
always @(cntB or cmpB) begin
    if (cntB < cmpB)    PWMB = 1'b0;
    else		PWMB = 1'b1;
end
always @(cntC or cmpC) begin
    if (cntC < cmpC)    PWMC = 1'b0;
    else		PWMC = 1'b1;
end

/************************************************************************
 *    PWMクロック用プリスケーラ                                         *
 *        8bit PWM 出力                                                 *
 *        分解能 : 8bit                                                 *
 *        基本周期 : 5KHz(200usec)                                      *
 *                   クロック = 1.28MHz                                 *
 *    プリスケーラクロック                                              *
 *        1bit(1/2) : 10MHz                                             *
 *        2bit(1/4) :  5MHz                                             *
 *        3bit(1/8) :  2.5MHz                                           *
 *        4bit(1/16):  1.25MHz                                          *
 ************************************************************************/
always @(posedge SCLOCK or negedge SRESET) begin
    if (~SRESET)	clkcnt = 'b0;
    else		clkcnt = clkcnt + 1;
end

assign	CLKOUT = clkcnt[1];

endmodule
/* end of file */